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semiconductor group 1 12.97 ? 8 388 608 words by 4-bit organization ? 0 to 70 c operating temperature ? hyper page mode - edo - operation ? performance: ? single + 3.3 v ( 0.3v) power supply ? low power dissipation: max. 306 active mw ( hyb 3164805bj/bt(l)-40) max. 252 active mw ( hyb 3164805bj/bt(l)-50) max. 216 active mw ( hyb 3164805bj/bt(l)-60) max. 486 active mw ( hyb 3165805bj/bt(l)-40) max. 396 active mw ( hyb 3165805bj/bt(l)-50) max. 324 active mw ( hyb 3165805bj/bt(l)-60) 7.2 mw standby (lvttl) 3.6 mw standby (lvmos) 720 m a standby for l-version ? read, write, read-modify-write, cas -before-ras refresh (cbr), ras -only refresh, hidden refresh ? self refresh (l-version only) ? 8192 refresh cycles/128 ms , 13 r/ 10c addresses (hyb 3164805bj/bt) 4096 refresh cycles/ 64 ms , 12 r/ 11c addresses (hyb 3165805bj/bt) ? 128 msec refresh period for l-versions ? plastic package: p-soj-32-1 400 mil hyb 3164(5)400bj p-tsopii-32-1 400 mil hyb 3164(5)400bt(l) -40 -50 -60 t rac ras access time 40 50 60 ns t cac cas access time 10 13 15 ns t aa access time from address 20 25 30 ns t rc read/write cycle time 69 84 104 ns t hpc hyper page mode (edo) cycle time 16 20 25 ns hyb 3164805bj/bt(l) -40/-50/-60 hyb 3165805bj/bt(l) -40/-50/-60 8m x 8-bit dynamic ram (4k & 8k refresh, edo-version) premininary information
semiconductor group 2 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram this hyb3164(5)805b is a 64 mbit dynamic ram organized 8 388 608 by 8 bits. the device is fabricated in siemens most advanced 0,25 m m-cmos silicon gate process technology. the circuit and process design allow this device to achieve high performance and low power dissipation. the hyb3164(5)805b operates with a single 3.3 +/-0.3v power supply and interfaces with either lvttl or lvcmos levels. multiplexed address inputs permit the hyb 3164(5)400b to be packaged in a 400mil wide soj-32 or tsop-32 plastic package. these packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment.the hyb3164(5)805btl parts have a very low power ?sleep mode supported by self refresh. ordering information type ordering code package descriptions 8k-refresh versions: hyb 3164805bj-40 p-soj-32-1 400 mil dram (access time 40 ns) hyb 3164805bj-50 p-soj-32-1 400 mil dram (access time 50 ns) hyb 3164805bj-60 p-soj-32-1 400 mil dram (access time 60 ns) hyb 3164805bt-40 p-tsopii-32-1 400 mil dram (access time 40 ns) hyb 3164805bt-50 p-tsopii-32-1 400 mil dram (access time 50 ns) hyb 3164805bt-60 p-tsopii-32-1 400 mil dram (access time 60 ns) hyb 3164805btl-50 p-tsopii-32-1 400 mil dram (access time 50 ns) hyb 3164805btl-60 p-tsopii-32-1 400 mil dram (access time 60 ns) 4k-refresh versions : hyb 3165805bj-40 p-soj-32-1 400 mil dram (access time 40 ns) hyb 3165805bj-50 p-soj-32-1 400 mil dram (access time 50 ns) hyb 3165805bj-60 p-soj-32-1 400 mil dram (access time 60 ns) hyb 3165805bt-40 p-tsopii-32-1 400 mil dram (access time 40 ns) hyb 3165805bt-50 p-tsopii-32-1 400 mil dram (access time 50 ns) hyb 3165805bt-60 p-tsopii-32-1 400 mil dram (access time 60 ns) hyb 3165805btl-50 p-tsopii-32-1 400 mil dram (access time 50 ns) hyb 3165805btl-60 p-tsopii-32-1 400 mil dram (access time 60 ns)
semiconductor group 3 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram pin configuration pin names a0-a12 address inputs for 8k-refresh version hyb 3164805bj/bt(l) a0-a11 address inputs for 4k-refresh version hyb 3165805bj/bt(l) ras row address strobe oe output enable i/o1-i/o8 data input/output cas column address strobe we read/write input vcc power supply ( + 3.3v) vss ground p-soj-32-1 (400 mil) * pin 24 is a12 for hyb 3164805bj/bt(l) and n.c. for hyb 3165805bj/bt(l) p-tsopii-32-1 (400 mil) 1 2 3 4 5 6 9 10 11 12 13 14 23 24 25 26 27 28 vss i/o8 i/o7 i/o6 i/o5 cas vcc i/o1 i/o2 i/o3 a0 a1 a2 a3 vcc 18 19 20 o oe we i/o4 7 22 21 8 ras 15 16 n.c. vcc . a4 a5 32 31 30 29 vss a12 / n.c. * a11 a10 a9 a8 a7 a6 vss 17
semiconductor group 4 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram truth table function ras cas we oe row addr col addr i/o1- i/o4 standby h h - x x x x x high impedance read l l h l row col data out early-write l l l x row col data in delayed-write l l h - l h row col data in read-modify-write l l h - l l - h row col data out, data in hyper page mode read 1st cycle l h - l h l row col data out 2nd cycle l h - l h l n/a col data out hyper page mode write 1st cycle l h - l l x row col data in 2nd cycle l h - l l x n/a col data in hyper page mode rmw 1st cycle l h - l h - l l - h row col data out, data in 2st cycle l h - l h - l l - h n/a col data out, data in ras only refresh l h x x row n/a high impedance cas -before-ras refresh h - l l h x x n/a high impedance test mode entry h - l l l x x n/a high impedance hidden refresh read l-h-l l h l row col data out write l-h-l l l x row col data in self refresh (l-version only) h - l l h x x x high impedance
semiconductor group 5 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram block diagram for hyb 3164805bj/bt(l) no. 2 clock generator column address buffer(10) refresh controller refresh counter (13) address buffers(13) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 8192 x 1024 x 8 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we cas 8192 1024 x8 . ras 10 13 8 i/o1 i /o2 oe 13 13 a10 a11 8 8 10 i/o8 a12
semiconductor group 6 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram block diagram for hyb 3165805bj/bt(l) no. 2 clock generator column address buffer(11) refresh controller refresh counter (12) address buffers(12) row no. 1 clock generator & data in buffer data out buffer column decoder sense amplifier i/o gating memory array 4096 x 2048 x 8 row decoder a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 we cas 4096 2048 x8 . ras 11 12 8 i/o1 i /o2 oe 12 12 a10 a11 8 8 11 i/o8
semiconductor group 7 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram absolute maximum ratings operating temperature range.............................................................................................. 0 to 7 0 c storage temperature range......................................................................................... C 55 to 150 c input/output voltage.................................................................................. -0.5 to min (vcc+0.5,4.6) v power supply voltage.................................................................................................... -0.5v t o 4.6 v power dissipation.............................................................................................................. . .....0.62 w data out current (short circuit)............................................................................................... . ..50 ma note stresses above those listed under ?absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may effect device reliability. dc characteristics t a = 0 to 70 c, v ss = 0 v, v cc = 3.3 v 0.3 v parameter symbol limit values unit note min. max. input high voltage v ih 2.0 vcc+0.3 v 1) input low voltage v il C 0.3 0.8 v 1) output high voltage (lvttl) output ?h level voltage (iout = -2ma) v oh 2.4 C v output low voltage (lvttl) output ?llevel voltage (iout = +2ma) v ol C0.4v output high voltage (lvcmos) output ?h level voltage (iout = -100ua) v oh vcc-0.2 - v ouput low voltage (lvcmos) output ?l level voltage (iout = +100ua) v ol - 0.2 v input leakage current,any input (0 v < vin < vcc , all other pins = 0 v i i(l) C 2 2 m a output leakage current (do is disabled, 0 v < vout < vcc ) i o(l) C 2 2 m a
semiconductor group 8 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram dc-characteristics (cont d) t a = 0 to 70 c, v ss = 0 v, v cc = 3.3 v 0.3 v parameter symbol refresh version unit note 4k row 8k row operating current -40 ns version -50 ns version - -60 ns version (ras , cas , address cycling: trc = trc min.) i cc1 135 110 90 85 70 60 ma ma ma 2) 3) 4) standby current ( ras = cas = vih ) i cc2 22maC ras only refresh current: - -40 ns version -50 ns version -60 ns version (ras cycling: cas = vih: trc = trc min.) i cc3 135 110 90 85 70 60 ma ma ma 2) 4) hyper page mode (edo) current: -40 ns version -50 ns version -60 ns version (ras = v il , cas , address cycling: thpc=thpc min.) i cc4 100 65 45 100 65 45 ma ma 2) 3) 4) standby current ( ras = cas = vcc-0.2v ) i cc5 11maC standby current (l-version) (ras =cas = vcc-0.2v) i cc5 200 200 m aC cas before ras refresh current -40 ns version -50 ns version -60 ns version (ras , cas cycling: trc = trc min.) i cc6 135 110 90 85 70 60 ma ma 2) 4) self refresh current (l-version only) (cbr cycle with tras>trassmin, cas held low, we = vcc-0.2v, address and din=vcc-0.2v or 0.2v) i cc7 400 400 m a capacitance t a = 0 to 70 c, v cc = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit min. max. input capacitance (a0 to a11,a12) c i1 C5pf input capacitance (ras , cas , we , oe ) c i2 C7pf i/o capacitance (i/o1-i/o8) c io C7pf
semiconductor group 9 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram ac characteristics 5)6) ac64-2e t a = 0 to 70 c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note - 40 - 50 - 60 min. max. min. max. min. max. common parameters random read or write cycle time t rc 69 C 84 C 104 C ns ras pulse width t ras 40 100k 50 100k 60 100k ns cas pulse width t cas 6 100k 8 100k 10 100k ns ras precharge time t rp 25 C 30 C 40 C ns cas precharge time t cp 6C8C10Cns row address setup time t asr 0C0C0Cns row address hold time t rah 5C7C10Cns column address setup time t asc 0C0C0Cns column address hold time t cah 5C7C10Cns ras to cas delay time t rcd 9 3011371445ns ras to column address delay time t rad 7 20 9 25 12 30 ns ras hold time t rsh 6C8 10Cns cas hold time t csh 32 C 40 48 C ns cas to ras precharge time t crp 5C5C5Cns transition time (rise and fall) t t 150150150ns7 refresh period for 8k-refresh-version t ref C 128 C 128 C 128 ms refresh period for 4k-refresh version t ref C64C64C64ms refresh period for l-versions t ref C 128 C 128 C 128 ms read cycle access time from ras t rac C40C50C60ns8, 9 access time from cas t cac C10C13C15ns8, 9 access time from column address t aa C 20 C 25 C 30 ns 8,10 oe access time t oea C10C13C15ns column address to ras lead time t ral 20 C 25 C 30 C ns read command setup time t rcs 0C0C0Cns read command hold time t rch 0C0C0Cns11
semiconductor group 10 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram read command hold time referenced to ras t rrh 0C0C0Cns11 cas to output in low-z t clz 0C0C0Cns8 output buffer turn-off delay t off 010013015ns12 output buffer turn-off delay from oe t oez 010013015ns12 data to cas low delay t dzc 0C0C0Cns13 data to oe low delay t dzo 0C0C0Cns13 cas high to data delay t cdd 10 C 13 C 15 C ns 14 oe high to data delay t odd 10 C 13 C 15 C ns 14 write cycle write command hold time t wch 5C7C10Cns write command pulse width t wp 5C7C10Cns write command setup time t wcs 0C0C0Cns15 write command to ras lead time t rwl 6C8C10Cns write command to cas lead time t cwl 6C8C10Cns data setup time t ds 0C0C0Cns16 data hold time t dh 5C7C10Cns16 read-modify-write cycle read-write cycle time t rwc 89 C 109 C 133 C ns ras to we delay time t rwd 52 C 65 C 77 C ns 15 cas to we delay time t cwd 22 C 28 C 32 C ns 15 column address to we delay time t awd 32 C 40 C 47 C ns 15 oe command hold time t oeh 5C7C10Cns hyper page mode (edo) cycle hyper page mode (edo) cycle time t hpc 16 C 20 C 24 C ns access time from cas precharge t cpa C22C27C32ns7 output data hold time t coh 3C5C5Cns ac characteristics (cont d) 5)6) ac64-2e t a = 0 to 70 c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note - 40 - 50 - 60 min. max. min. max. min. max.
semiconductor group 11 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram ras pulse width in hyper page mode t ras 40 200k 50 200k 60 200k ns cas precharge to ras delay t rhpc 22 C 27 C 32 C ns oe pulse width t oep 5C5C5Cns oe hold time from cas high t oehc 5C5C5Cns output buffer turn-off delay from we t wez 010013015ns oe setup time prior to cas t oes 5C5C5Cns hyper page mode (edo) read- modify-write cycle hyper page mode (edo) read-write cycle time t prwc 44 C 54 C 63 C ns cas precharge to we t cpwd 34 C 42 C 49 C ns cas before ras refresh cycle cas setup time t csr 5C5C5Cns cas hold time t chr 5C5C10Cns ras to cas precharge time t rpc 5C5C5Cns write to ras precharge time t wrp 5C5C10Cns write hold time referenced to ras t wrh 5C5C10Cns self refresh cycle (l-versions only) ras pulse width t rass 100k 100k _ 100 k_ ns17 ras precharge time t rps 69 C 84 C 104 C ns 17 cas hold time t chs -50 C -50 C -50 C ns 17 test mode cycle write command setup time t wts 5C5C5Cns18 write command hold time t wth 5C5C5Cns18 ac characteristics (cont d) 5)6) ac64-2e t a = 0 to 70 c, v cc = 3.3 v 0.3v , t t = 2 ns parameter symbol limit values unit note - 40 - 50 - 60 min. max. min. max. min. max.
semiconductor group 12 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram notes: 1) all voltages are referenced to vss. vih may overshoot to vcc + 2.0 v for pulse widths of < 4ns with 3.3v. vil may undershoot to -2.0v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. 2) icc1, icc3, icc4 and icc6 and icc7 depend on cycle rate. 3) icc1 and icc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = vil. in the case of icc4 it can be changed once or less during a hyper page mode cycle ( thpc). 5) an initial pause of 100 m s is required after power-up followed by 8 ras -only-refresh cycles, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 2 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. also, transition times are measured between vih and vil. 8) measured with the specified current load and 100 pf at voh = 2.0 v and vol = 0.8 v. 9) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 10) operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 11) either trch or trrh must be satisfied for a read cycle. 12) toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13) either tdzc or tdzo must be satisfied. 14) either tcdd or todd must be satisfied. 15) twcs, trwd, tcwd, tawd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 16) these parameters are referenced to cas leading edge in early write cycles and to write leading edge in read-modify-write cycles. 17) when using self refresh mode, the following refresh operations must be performed to ensure proper dram operation: if row addresses are being refresh in an evenly distributed manner over the refresh interval using cbr refresh cycles, then only one cbr cycle must be performed immediatly after exit from self refresh. if row addresses are being refresh in any other manner (ror - distributed/burst or cbr-burst) over the refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey after exit from self refresh 18) in a test mode read cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value. these parameters must be adjusted in test mode cycles by adding 5ns to the specified value. associated timings must be adjusted by 5 ns.
semiconductor group 13 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram read cycle row column row valid data out ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t aa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z h o r l wl1
semiconductor group 14 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram write cycle (early write) ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t rc t csh t rad t cas t rp t crp t rsh t rcd t ral t asr t cah t asr t cwl t rwl t wp t asc t wch valid data in t ds t dh hi z column row row t rah t wcs h o r l wl2
semiconductor group 15 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram write cycle (oe controlled write) valid data t rwl t wp t oeh t odd t cwl t dzo t oea t clz t ds t oez t dh t rc v ih v il row t dzc h o r l hi-z hi-z column row t asc t rad t ral t cah t rah ras cas address we oe i/o (inputs) i/o (outputs) v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol . t ras t csh t cas t rp t crp t rsh t rcd t asr t asr wl3
semiconductor group 16 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram read-write (read-modify-write) cycle row row t csh t cas t crp t rwc t awd t asr t rp t ras t rah t cah i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il t asr column t rcd t dh t rsh t rad t cwd t oeh t rwd t rwl t cwl t clz t wp t rcs t aa t oea t ds t dzc t dzo t odd t cac t oez valid data in data out t rac h o r l t asc v ih v il v ih v il ras cas address v ih v il wl4
semiconductor group 17 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hyper page mode (edo) read cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h o r l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhpc t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t coh t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 t coh n wl5
semiconductor group 18 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hyper page mode (edo) read cycle (oe control) t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h o r l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhcp t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t oez t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 n t oep t oehc t oea t oep t oehc t oez t oea wl6
semiconductor group 19 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hyper page mode (edo) read cycle (we control) t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data out ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h o r l v oh v ol oe t ras t crp t asc t hpc t cah t rad t rhpc t asc t rcs t rrh t rch (output) t rac t aa t cac t clz t oea t oes t wez t cac t aa t cpa data out column n column 1 data out t oez t off t cac t aa t cpa 1 2 n t rch t rcs t wp t rch t rcs t wp t wez wl7
semiconductor group 20 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hyper page mode (edo) early write cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t cwl t wcs t wp t wch t csh t cas t rcd t rah t asr t dh t ds t dh t ds column 1 column 2 row addr data in n data in 2 data in 1 column n ras i/o (input) we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h o r l v oh v ol oe t ras t crp t asc t cwl t wcs t wp t wch t cwl t wcs t wp t wch t rwl t dh t ds t hpc t cah t rad t rhpc t asc wl8
semiconductor group 21 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hyper page mode (edo) late write cycle t rp t rsh t cas t cas t cp t crp t ral t cah t cah t asc t csh t cas t rcd t rah t asr column 2 row data in ras i/o we address cas v ih v il v ih v il v ih v il v ih v il v ih v il h o r l v oh v ol oe t ras t crp t asc t hpc t cah t rad t asc t rcs (input) t odd t dh data in column n column 1 data in t oeh 1 2 n t wp t rcs t wp wl16 cp t t ds t dh t ds t wp t ds t dh t rcs t cwl t cwl t cwl t rwl t odd t oeh t odd t oeh
semiconductor group 22 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hyper page mode (edo) read-modify-write cycle t cah t cp t dzc t dzo t rac t cac t clz t rcs t aa t oea t rcd t rad t rah t asr t asc t cas t cas t prwc t cwd t cah t asc t cas t rsh t rp t crp t asr t cah t asc t ral t cwd t rwd t cwl t cwl t cwd t awd t awd t wp t wp t cwl t rwl t awd t wp t odd t oeh t dh t ds t cpa t oez t clz t dzc t aa t cac t oea t ds t oez t dh t oeh t aa t odd t dzc t cpa t oea t clz t ds t dh t oeh t odd ras v ih v il cas v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column column row t rasp t csh column t cpwd t cpwd wl17
semiconductor group 23 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram ras only refresh cycle t crp t rah t rp t ras t rc t asr t asr t rpc v ih v il v ih v il v ih v il v oh v ol row row hi-z address ras cas i/o (outputs) h o r l wl9
semiconductor group 24 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram cas -before-ras refresh cycle t rp t ras t rp t rc t crp t cp t rpc t chr t wrh t wrp t csr t rpc t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h o r l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol wl10
semiconductor group 25 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hidden refresh read cycle ras i/o (outputs) i/o (inputs) oe we address cas t rc t rc t ras t ras t rp t rp t crp t chr t rad t cah t asc t rah t asr t asr t rcs t rrh t aa t dzc t dzo t cac t rac t clz t oez t off t odd t cdd t rcd t rsh t oea v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il t wrp t wrh h o r l valid data out row column row hi-z v oh v ol wl11
semiconductor group 26 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram hidden refresh early write cycle ras i/o (output) i/o (input) we address v ih v il v ih v il v ih v il cas v ih v il v ih v il h o r l t rc t ras t rcd t rsh t rad t cah t wcs t wch t wp t asr t rah t ds t dh t asr t crp t chr t rp t ras t rc t rp t asc row row valid data hi-z column v oh v ol t wrp t wrh wl12
semiconductor group 27 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram self refresh (sleep mode) t rps t rass t rp t crp t cp t rpc t wrh t wrp t csr t off t oez t cdd t odd v ih v il v ih v il v ih v il v ih v il v ih v il hi-z h o r l ras i/o (outputs) i/o (inputs) oe we cas v oh v ol t chs wl13
semiconductor group 28 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram test mode entry cycle t rc t ras t rp t rpc t crp t chr t wth t rpc t rp t cp t csr t wts t cdd t off t oez t odd i/o (outputs) v oh v ol v ih v il v ih v il i/o (inputs) oe we v ih v il cas ras v ih v il v ih v il h o r l hi-z address t rah t asr v ih v il row wl15 hi-z
semiconductor group 29 hyb3164(5)805bj/bt(l)-40/-50/-60 8m x 8-dram package outlines plastic package p-soj-32-1 (400 mil) (small outline j-lead, smd) plastic package p-tsopii-32-1 (400 mil) (small outline j-lead, smd)

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